1. Field of the Invention
This application relates to integrated circuit devices and more particularly to frequency margin testing of integrated circuit devices.
2. Description of the Related Art
High-performance (i.e., high-speed and low jitter) system applications such as Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), or 10 Gigabyte Ethernet (10 GbE) typically use precision timing sources to transmit, receive and perform other data processing functions on a communication data stream. Clocks based on high Q elements, e.g. crystal oscillators, surface acoustic wave (SAW) oscillators, ceramic oscillators, and micro-electro mechanical system (MEMS) oscillators may be used to generate low jitter, high frequency timing signals. However, clocks generated from high Q elements typically have fixed frequencies or may vary only a few hundred ppm away from nominal frequencies.
The substantially fixed frequency nature of such clocks presents a challenge for testing circuits dependent on those clocks over a suitable frequency range to guarantee design timing margin. Frequency margin testing of circuits on a typical communications system board may utilize duplicate fixed frequency oscillators, selectable via a high-speed multiplexer. During testing, the multiplexer is controlled to run the system board at nominal, nominal plus margin, and nominal minus margin rates by selecting appropriate ones of the fixed frequency oscillators. A typical margin may be approximately 10 percent of the nominal rate. Correct system operation for all three clock rates is believed to guarantee adequate timing margin.
This approach includes multiple oscillators on the system board, increasing component costs and board area, yet only one of these multiple oscillators is used during normal operation of the system board. The high-speed multiplexer logic for switching between clock sources increases component costs and board area. Furthermore, the number of clock sources included on the board generally determines the number of predetermined frequencies that may be used for testing the frequency margin. In general, the board cannot be stressed until failure to determine an actual frequency margin for the board.
Another approach for frequency margin testing introduces externally generated test clocks during board testing. This approach typically dedicates board space for probe points to allow connection of an external clock source. These probe points can degrade the transmission line characteristics of the board traces and lower clock performance. In addition, one or more external, high-performance, frequency agile clock sources may be used for board testing, thus increasing costs, especially for concurrent testing of multiple boards.
Accordingly, improved techniques for performing frequency margin testing of communications system circuit boards are desired.